remove unnecessary barriers in hercules/vic.S, add comments

This commit is contained in:
Chris Copeland 2024-03-25 09:39:48 -07:00
parent 33b25314c9
commit b731a2e3f8
Signed by: chrisnc
GPG Key ID: 14550DA72485DF30
1 changed files with 18 additions and 19 deletions

View File

@ -22,37 +22,36 @@
* (+/-) 8-bit immediate offsets to access both the VIM and SSI registers. */
#define SYS_BASE 0xFFFFFF00
.macro mask_ssi
// Mask the software interrupt in the VIM.
.macro vic_svc_start
mov r12, SYS_BASE
mov lr, SSI_CHANNEL_BITMASK
str lr, [r12, SSI_REQENACLR - SYS_BASE]
.endm
.macro vic_svc_start
mask_ssi
/* Force any pending syscall IRQ to be executed immediately when interrupts
* are re-enabled, rather than after the syscall handler may have called
* rt_syscall_run already. */
dsb
isb
/* A read-back from the VIM and an isb are ordinarily needed when masking
* an interrupt channel to ensure that it has taken effect and to take any
* latched interrupts before proceeding. In this case we are masking the
* SSI interrupt and it is only triggered by a write. Because the SSI
* registers and VIM must have either device or strongly-ordered semantics,
* any SSI triggered after this point and before vic_svc_finish will be
* masked. */
.endm
.macro vic_svc_finish
// Unmask the software interrupt in the VIM.
mov r2, SYS_BASE
mov r3, SSI_CHANNEL_BITMASK
str r3, [r2, SSI_REQENASET - SYS_BASE]
mov r0, SYS_BASE
mov r1, SSI_CHANNEL_BITMASK
str r1, [r0, SSI_REQENASET - SYS_BASE]
.endm
/* The Hercules VIM doesn't automatically mask the active interrupt, so we need
* to mask and unmask it manually just like the svc handler. */
.macro vic_syscall_irq_start
mask_ssi
/* Clear the software interrupt. This must happen after it is masked, so if
* it is triggered again after interrupts are re-enabled, it won't cause
* another syscall IRQ until after the current one is finished. */
ldr r0, [r12, SSIVEC - SYS_BASE]
mov r0, SYS_BASE
mov r1, SSI_CHANNEL_BITMASK
str r1, [r0, SSI_REQENACLR - SYS_BASE]
/* Clear the software interrupt so it can be triggered again. Any
* additional trigger will be masked until the current syscall IRQ handler
* returns. */
ldr r0, [r0, SSIVEC - SYS_BASE]
.endm
.macro vic_syscall_irq_finish