always align IRQ handlers by 4 bytes, use RT_IRQ_DEFAULT_ISA in sitara/vim nested IRQs

This commit is contained in:
Chris Copeland 2024-06-07 00:03:19 -07:00
parent a08d7223a5
commit 17badaaa10
Signed by: chrisnc
GPG Key ID: 14550DA72485DF30
5 changed files with 10 additions and 26 deletions

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@ -1,9 +1,5 @@
#pragma once
/* The Hercules VIM requires IRQ handler addresses to be 4-byte aligned, even
* if they are thumb-encoded. (The least-significant 2 bits are ignored.) */
#define RT_VIC_IRQ_ALIGN 4
/* The SSI should be routed to channel 126, which is the lowest priority.
* This maps to bit 30 of the REQENA*3 registers.
* Note: this is not the SSI's default VIM channel. */

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@ -1,9 +1,5 @@
#pragma once
/* The Sitara VIM requires IRQ handler addresses to be 4-byte aligned, even if
* they are thumb-encoded. (The least-significant 2 bits are ignored.) */
#define RT_VIC_IRQ_ALIGN 4
// The SW IRQ is ID 129 on AM263x. Override it if needed.
#ifndef RT_VIM_SW_IRQ
#define RT_VIM_SW_IRQ 129
@ -32,8 +28,6 @@ static inline void vic_syscall_pend(void)
vim_set(RT_VIM_SW_IRQ);
}
rt_static_assert(VIM_IRQ_ALIGN == RT_VIC_IRQ_ALIGN,
"RT_VIC_IRQ_ALIGN is incorrect");
rt_static_assert((uintptr_t)VIM == RT_VIM, "RT_VIM is incorrect");
rt_static_assert((uintptr_t)&VIM->irqvec == RT_VIM + RT_VIM_IRQVEC_OFFSET,
"RT_VIM_IRQVEC_OFFSET is incorrect");

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@ -1,6 +1,7 @@
#pragma once
#include <rt/arch/fp.h>
#include <rt/arch/irq.h>
#include <rt/arch/mode.h>
#include <stddef.h>
@ -28,8 +29,8 @@ struct vim
uint32_t prifiq;
uint32_t irqgsts;
uint32_t fiqgsts;
uint32_t irqvec;
uint32_t fiqvec;
void (*irqvec)(void);
void (*fiqvec)(void);
uint32_t actirq;
uint32_t actfiq;
uint32_t irqprimsk;
@ -45,8 +46,6 @@ struct vim
#define VIM ((volatile struct vim *)0x50F00000UL)
#define VIM_IRQ_ALIGN 4
#define VIM_BIT_SET(field, i) \
do \
{ \
@ -144,8 +143,8 @@ static inline void vim_set_ded_handler(void (*handler)(void))
*/
#define VIM_IRQ_HANDLER_NESTING_NOFP(fn) \
__attribute__((naked, target("general-regs-only"), \
aligned(VIM_IRQ_ALIGN))) void \
__attribute__((naked, target("general-regs-only", RT_IRQ_DEFAULT_ISA), \
aligned(4))) void \
fn(void) \
{ \
__asm__("sub lr, #4;" \
@ -171,7 +170,8 @@ static inline void vim_set_ded_handler(void (*handler)(void))
#if RT_ARM_FP
#define VIM_IRQ_HANDLER_NESTING_FP(fn) \
__attribute__((naked, aligned(VIM_IRQ_ALIGN))) void fn(void) \
__attribute__((naked, target(RT_IRQ_DEFAULT_ISA), aligned(4))) void \
fn(void) \
{ \
__asm__("sub lr, #4;" \
"srsdb sp!, %[mode_svc];" \

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@ -143,9 +143,7 @@ rt_svc_handler:
.section .text.rt_syscall_irq_handler,"ax",%progbits
.global rt_syscall_irq_handler
.type rt_syscall_irq_handler, %function
#ifdef RT_VIC_IRQ_ALIGN
.balign RT_VIC_IRQ_ALIGN
#endif // RT_VIC_IRQ_ALIGN
.balign 4
rt_syscall_irq_handler:
sub lr, 4
srsdb sp!, MODE_SYS

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@ -4,8 +4,6 @@
#include <rt/arch/fp.h>
#include <rt/arch/profile.h>
#include <vic.h>
#ifndef RT_IRQ_DEFAULT_ISA
/* IRQs can be hardware-vectored, and the default state for exception entry can
* be set to thumb, so choose the default based on whether we are compiling for
@ -47,8 +45,7 @@
_Pragma("GCC diagnostic push"); \
_Pragma("GCC diagnostic ignored \"-Wattributes\""); \
__attribute__((interrupt(interrupt_type), \
target("general-regs-only", isa), \
aligned(RT_VIC_IRQ_ALIGN))) void \
target("general-regs-only", isa), aligned(4))) void \
fn(void) \
{ \
uint32_t old_cpacr = cpacr(); \
@ -72,8 +69,7 @@
_Pragma("GCC diagnostic push"); \
_Pragma("GCC diagnostic ignored \"-Wattributes\""); \
__attribute__((interrupt(interrupt_type), \
target("general-regs-only", isa), \
aligned(RT_VIC_IRQ_ALIGN))) void \
target("general-regs-only", isa), aligned(4))) void \
fn(void); \
_Pragma("GCC diagnostic pop"); \
void fn(void)